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Bibliography

1
A. Raghunathan, N. K. Jha, and S. Dey,
High-level Power Analysis and Optimization,
Kluwer Academic Publisher, Norwell, MA, 1998.

2
R. Mehra, L. M. Guerra, and J. M. Rabaey,
``Low-power architectural synthesis and the impact of exploiting locality,''
J. VLSI Signal Processing, vol. 13, no. 8, pp. 877-88, Aug. 1996.

3
L. Goodby, A. Orailoglu, and P. M. Chau,
``Microarchitecture synthesis of performance-constrained, low power VLSI designs,''
in Proc. Int. Conf. Computer Design, Oct. 1994, pp. 323-326.

4
A. Dasgupta and R. Karri,
``Simultaneous scheduling and binding for power minimization during microarchitecture synthesis,''
in Proc. Int. Symp. Low Power Design, Apr. 1994, pp. 255-270.

5
J. M. Chang and M. Pedram,
``Register allocation and binding for low power,''
in Proc. Design Automation Conf., June 1995, pp. 29-35.

6
N. Kumar, S. Katkoori, L. Rader, and R. Vemuri,
``Profile-driven behavioral synthesis for low power VLSI systems,''
IEEE Design & Test Comput., pp. 70-84, Sept. 1995.

7
A. P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. Brodersen,
``Optimizing power using transformations,''
IEEE Trans. Computer-Aided Design, vol. 14, no. 1, pp. 12-51, Jan. 1995.

8
R. S. Martin and J. P. Knight,
``Power profiler: Optimizing ASICs power consumption at the behavioral level,''
in Proc. Design Automation Conf., June 1995, pp. 42-47.

9
M. Johnson and K. Roy,
``Optimal selection of supply voltages and level conversion during datapath scheduling under resource constraints,''
in Proc. Int. Conf. Computer Design, Oct. 1996, pp. 72-77.

10
A. Raghunathan and N. K. Jha,
``SCALP: An iterative-improvement-based low power data path synthesis system,''
IEEE Trans. Computer-Aided Design, vol. 16, no. 11, pp. 1260-1277, Nov. 1997.

11
K. S. Khouri, G. Lakshminarayana, and N. K. Jha,
``High-level synthesis of low power control-flow intensive circuits,''
IEEE Trans. Computer-Aided Design, vol. 18, no. 12, pp. 1715-1729, Dec. 1999.

12
D. Liu and C. Svensson,
``Power consumption estimation in CMOS VLSI chips,''
IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 663-670, June 1994.

13
J. Cong,
``A interconnect-centric design flow for nanometer technologies,''
Proc. IEEE, vol. 89, no. 4, pp. 505-528, Apr. 2001.

14
D. D. Gajski, N. D. Dutt, A. Wu, and S. T. Lin,
High-level Synthesis: Introduction to Chip Design,
Kluwer Academic Publisher, Norwell, MA, 1992.

15
M. R. Stan and W. P. Burleson,
``Low-power encoding for global communication in CMOS VLSI,''
IEEE Trans. VLSI Systems, vol. 5, no. 4, pp. 49-58, Dec. 1997.

16
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj,
``A coding framework for low-power address and data busses,''
IEEE Trans. VLSI Systems, vol. 7, no. 2, pp. 212-221, June 1999.

17
P. P. Sotiriadis and A. Chandrakasan,
``Low power bus coding techniques considering inter-wire capacitances,''
in Proc. Custom Integrated Circuits Conf., May 2000, pp. 507-510.

18
S. Hong and T. Kim,
``Bus optimization for low-power data path synthesis based on network flow method,''
in Proc. Int. Conf. Computer-Aided Design, Nov. 2000, pp. 312-317.

19
P. G. Paulin and J. P. Knight,
``Scheduling and binding algorithms for high-level synthesis,''
in Proc. Design Automation Conf., June 1989, pp. 1-6.

20
C. A. Papachristou and H. Konuk,
``A linear program driven scheduling and allocation method followed by an interconnect optimization algorithm,''
in Proc. Design Automation Conf., June 1990, pp. 77-83.

21
T. A. Ly, W. L. Elwood, and E. F. Girczyc,
``A generalized interconnect model for data path synthesis,''
in Proc. Design Automation Conf., June 1990, pp. 168-173.

22
E. D. Lagnese and D. E. Thomas,
``Architectural partition for system level synthesis of integrated circuits,''
IEEE Trans. Computer-Aided Design, vol. 10, no. 7, pp. 847-860, July 1991.

23
C. Monahan and F. Brewer,
``Communication driven interconnection synthesis,''
in Proc. 6th Int. Workshop High-level Synthesis, 1992.

24
C. Jego, E. Casseau, and E. Martin,
``Interconnect cost control during high-level synthesis,''
in Proc. Design Circuits & Integrated Systems Conf., Nov. 2000, pp. 507-512.

25
S. Tarafdar and M. Leeser,
``The DT-model: High-level synthesis using data transfers,''
in Proc. Design Automation Conf., June 1998, pp. 114-117.

26
M. C. McFarland and T. J. Kowalski,
``Incorporating bottom-up design into hardware synthesis,''
IEEE Trans. Computer-Aided Design, vol. 9, no. 9, pp. 938-950, Sept. 1990.

27
D. W. Knapp,
``Fasolt: A program for feedback-driven data-path optimization,''
IEEE Trans. Computer-Aided Design, vol. 11, no. 6, pp. 677-695, June 1992.

28
J.-P. Weng and A. C. Parker,
``3D scheduling: High-level synthesis with floorplanning,''
in Proc. Design Automation Conf., June 1992, pp. 668-673.

29
C. Ramachandran and F. J. Kurdahi,
``Combined topological and functionality based delay estimation using a layout-driven approach for high level applications,''
IEEE Trans. Computer-Aided Design, vol. 13, no. 12, pp. 1450-1460, Dec. 1994.

30
Y.-M. Fang and D. F. Wong,
``Simultaneous functional-unit binding and floorplanning,''
in Proc. Int. Conf. Computer-Aided Design, Nov. 1994, pp. 317-321.

31
V. G. Moshnyaga and K. Tamaru,
``A floorplan based methodology for data-path synthesis of sub-micron ASICs,''
IEICE Trans. Inf. & Syst., vol. E79-D, no. 10, 1996.

32
M. Xu and F. J. Kurdahi,
``Layout-driven RTL binding techniques for high-level synthesis using accurate estimators,''
ACM Trans. Design Automation Electronic Systems, vol. 2, no. 4, pp. 312-343, Oct. 1997.

33
P. Prabhakaran and P. Banerjee,
``Simultaneous scheduling, binding and floorplanning in high-level synthesis,''
in Proc. Int. Conf. VLSI Design, Jan. 1998, pp. 428-434.

34
K. Choi and S. P. Levitan,
``A flexible datapath allocation method for architectural synthesis,''
ACM Trans. Design Automation Electronic Systems, vol. 4, no. 4, pp. 376-404, Oct. 1999.

35
W. E. Dougherty and D. E. Thomas,
``Unifying behavioral synthesis and physical design,''
in Proc. Design Automation Conf., June 2000, pp. 756-761.

36
E. Mussoll and J. Cortadella,
``High-level synthesis techniques for reducing the activity of functional units,''
in Proc. Int. Symp. Low Power Design, Apr. 1995, pp. 99-104.

37
S. Dey, A. Raghunathan, N. K. Jha, and K. Wakabayashi,
``Controller-based power management for control-flow intensive designs,''
IEEE Trans. Computer-Aided Design, vol. 18, no. 10, pp. 1496-1508, Oct. 1999.

38
G. Lakshminarayana, A. Raghunathan, N. K. Jha, and S. Dey,
``Power management in high-level synthesis,''
IEEE Trans. VLSI Systems, vol. 7, no. 1, pp. 7-15, Mar. 1999.

39
Independent JPEG Group,
http://www.ijg.org.

40
K. R. Rao and P. Yip,
Discrete Cosine Transform,
Academic Press, London, 1990.

41
http://www.cbl.ncsu.edu/benchmarks/.

42
S.-Y. Kung,
VLSI Array Processors,
Prentice-Hall, Englewood Cliffs, NJ, 1987.

43
J. Cong and Z. Pan,
``Interconnect performance estimation models for design planning,''
IEEE Trans. Computer-Aided Design, vol. 20, no. 6, pp. 739-752, June 2001.

44
NEC cell-based ASIC CB-11,
http://www.necel.com/ASIC/, 2000.

45
A. Raghunathan,
Personal communication.

46
J. M. Rabaey,
Digital Integrated Circuits: A Design Perspective,
Prentice Hall, Englewood Cliffs, NJ, 1996.

47
T. Uchino and J. Cong,
``An interconnect energy model considering coupling effects,''
IEEE Trans. Computer-Aided Design, vol. 21, no. 7, pp. 763-776, July 2002.

48
C. N. Taylor, S. Dey, and Y. Zhao,
``Modeling and minimization of interconnect energy dissipation in nanometer technologies,''
in Proc. Design Automation Conf., June 2001, pp. 754-757.

49
P. P. Sotitriadis and A. Chandrakasan,
``A bus energy model for deep sub-micron technology,''
to appear in IEEE Trans. VLSI Systems.

50
P. Heydari and M. Pedram,
``Interconnect energy dissipation modeling in high-speed ULSI circuits,''
in Proc. Asia & South Pacific Design Automation Conf., Jan. 2002, pp. 132-137.

51
N. Sherwani,
Algorithms for VLSI Physical Design Automation: Second Edition,
Kluwer Academic Publishers, Norwell, MA, 1995.

52
C. M. Fiduccia and R. M. Mattheyses,
``A linear-time heuristic for improving network partition,''
in Proc. Design Automation Conf., June 1982, pp. 173-181.

53
H. B. Bakoglu,
Circuits, Interconnections, and Packaging for VLSI,
Addison-Wesley, Reading, MA, 1990.

54
P. Christie,
``A fractal analysis of interconnection complexity,''
Proc. IEEE, vol. 81, no. 10, pp. 1492-1499, Oct. 1993.

55
D. Sylvester and K. Keutzer,
``System-level performance modeling with $BACPAC$ - Berkeley advanced chip performance calculator,''
in Proc. Workshop on System-Level Interconnect Prediction, Apr. 1999, pp. 109-114.

56
J. A. Davis, V. K. De, and J. D. Meindl,
``A stochastic wire-length distribution for gigascale integration (GSI) - Part I: Derivation and validation,''
IEEE Trans. Eletronic Devices, vol. 45, no. 3, pp. 580-589, Mar. 1998.

57
J. A. Davis, V. K. De, and J. D. Meindl,
``A stochastic wire-length distribution for gigascale integration (GSI) - Part II: Application to clock frequency, power dissipation, and chip size estimation,''
IEEE Trans. Eletronic Devices, vol. 45, no. 3, pp. 590-597, Mar. 1998.

58
P. Kapur, G. Chandra, and K. C. Saraswat,
``Power estimation in global interconnects and its reduction using a novel repeater optimization methodology,''
in Proc. Design Automation Conf., June 2002, pp. 461-466.

59
B. S. Cherkauer and E. G. Friedman,
``A unified design methodology for CMOS tapered buffers,''
IEEE Trans. VLSI Systems, vol. 3, no. 1, pp. 99-111, Mar. 1995.

60
V. P. Roychowdhury, S. K. Rao, L. Thiele, and T. Kailath,
``On the localization of algorithms for VLSI processor arrays,''
in Proc. VLSI Signal Processing, III. pp. 459-470, IEEE Press, NY, 1988.

61
M. Munch, B. Wurth, R. Mehra, J. Sproch, and N. Wehn,
``Automating RT-level operand isolation to minimize power consumption in datapaths,''
in Proc. Design, Automation & Testing in Europe, Mar. 2000, pp. 624-631.

62
C.-T. Hsieh and M. Pedram,
``Architectural energy optimization by bus splitting,''
IEEE Trans. Computer-Aided Design, vol. 21, no. 4, pp. 408-414, Apr. 2002.

63
National Technology Roadmap for Semiconductors,
Semiconductor Industry Association, 1997.

64
H. C. Lin and L. W. Linholm,
``An optimized output stage for MOS integrated circuits,''
IEEE J. Solid-State Circuits, vol. SC-10, no. 2, pp. 106-109, Apr. 1975.

65
J.-S. Choi and K. Lee,
``Design of CMOS tapered buffer for minimum power-delay product,''
IEEE J. Solid-State Circuits, vol. 29, no. 9, pp. 1142-1145, Sept. 1994.


Lin Zhong 2003-10-11