RTL Interconnect Power Estimation

Circuit components visible at the RTL can be categorized into datapath units (DPUs), which generate or consume data, and interconnects, which route data between DPUs. RTL DPUs consist of functional units, registers, memory banks and controllers, $etc$. RTL interconnects consist of data transfer wires, buffers on the wires, clock distribution network and steering logic. Power, delay and area of interconnects within DPUs are considered by corresponding models for the DPUs provided in the RTL design library.